Today's designs for system-on-chip (SoC) may have more than one hundred embedded memories on a single chip. These memories may be scattered around the device instead of being concentrated in one location. Typically, these memories are of different types and sizes. In addition, these memories may be further embedded inside embedded cores. This structure poses a challenge to testing all of the memories on the chips, as test access may be limited to only a few input/output (I/O) pins.
Built in self-test (BIST) is frequently used to test such embedded memories within SoCs, as it provides a simple and low cost method of testing that does not affect performance. Specific testing may be required to test all of the memories on a device, which is known as memory built-in self-test (MBIST). As SoCs are used ever more widely in devices, such as mobile phones, the challenge becomes offering increased performance while maintaining a portable device. As devices gain performance and functionality, the number of memories to support that functionality grows, as does the need to test those memories. This may lead to congestion at the MBIST controller as all data path routing must pass through the controller.
In conventional memory test methodology test results are not captured concurrently with the testing process. Currently results are available only at the very end of test execution. This leads to a number of difficulties includes increased overhead caused by the serial shifting out of the pass/fail status, increased testing time, which may add 20% additional testing time, long running pre-silicon simulations, and higher debug and turn-around times.
The problem increases as memories grow ever larger. Larger memories may have as many as 64 output values that must be shifted out for every 100 memories being tested. The shifting out of results occurs in a serial, not parallel manner, which also increases the total test time. The increase may range form 5 ms to 20 ms per pattern.
There is a need in the art for a method and apparatus to overcome the limitation of reading out pass/fail signatures on test data output (TDO) pins serially at the end of testing.